Why does IRQ_HPD of the DisplayPort Intel® FPGA IP unexpectedly assert before a video source initiates link training? - Why does IRQ_HPD of the DisplayPort Intel® FPGA IP unexpectedly assert before a video source initiates link training? Description The DisplayPort Intel® FPGA IP Sink may assert CR_Lock due to receiver noise. The invalid CR_Lock may result in an incorrect IRQ_HPD assertion before the video source initiates link training. DisplayPort Intel® FPGA IP Source devices should ignore this incorrect IRQ_HPD assertion until link training begins. Resolution This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 17.1. Custom Fields values: ['novalue'] Troubleshooting 2205907583 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 13.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-07