Why is the eCPRI Intel® FPGA IP reset polarity inverted in platform designer? - Why is the eCPRI Intel® FPGA IP reset polarity inverted in platform designer? Description Due to a problem in the eCPRI Intel® FPGA IP version 2.0.4 and earlier, the input reset signal maps to incorrect polarity when instantiated in Platform Designer. The input reset to the eCPRI Intel® FPGA IP is active low, Platform Designer should automatically map the signal type to "reset_n" instead of reset. Resolution To work around this problem, perform the following steps: 1). Open the ecpri_interface.tcl file available at <quartus_instalation_dir>/ip/altera_cloud/ecpri/ecpri_hw_tcl/. 2). Find and replace the following line: From add_interface_port $port_name $port_name reset input 1 To add_interface_port $port_name $port_name reset_n input 1 This problem has been fixed starting in version 23.3 of the eCPRI Intel® FPGA IP webcore. Custom Fields values: ['novalue'] Troubleshooting 16021578521 False ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.1 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']