How to obtain the steady state values from IBIS model I-V curves to verify with the steady state values from V-T curves? - How to obtain the steady state values from IBIS model I-V curves to verify with the steady state values from V-T curves?
Description In the IBIS model, sometimes we encounter a warning of I-V and V-T mismatch when performing IBIS syntax checking. This warning is referring to the steady state voltage values found in the V-T curves such as rising and falling which are different from the steady state voltage values obtained from the I-V curves such as pullup and pulldown. Whenever the differences exceed certain limits as specified by the IBIS syntax checker, it will prompt warning or error Download this How-To document to learn how you can obtain the steady state values from IBIS model I-V curves to verify with the steady state values from V-T curves.
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Troubleshooting
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['FPGA Dev Tools Quartus II Software']
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No plan to fix
['Programmable Logic Devices']
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['novalue'] - 2022-01-19
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