PCI Express VHDL Example Design Simulation Fails - PCI Express VHDL Example Design Simulation Fails Description VHDL simulation fails for the example designs described in the Getting Started with the Arria V Hard IP for PCI Express chapter of the Arria V Hard IP for PCI Express User Guide and for “Getting Started with the Stratix V Hard IP for PCI Express” chapter of the Stratix V Hard IP for PCI Express User Guide . Resolution This issue is fixed in version 12.0 of the PCI Express IP cores. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.1 ['Arria® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']