Why is my multi-dimensional port split into individual single-bit ports in the gate-level simulation netlist? - Why is my multi-dimensional port split into individual single-bit ports in the gate-level simulation netlist? Description Due to a limitation in the Quartus® II software, for designs written in AHDL with Verilog HDL specified as the output simulation netlist format, multi-dimensional ports are split into individual single-bit ports in the output netlist. Resolution To work around this limitation, generate your output simulation netlist in VHDL instead of Verilog HDL. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25