Why is there a mismatch in Priority Flow Control (PFC) frame duration using the F-Tile Ethernet Hard IP variant configured for 400GE-8 or 400GE-4? - Why is there a mismatch in Priority Flow Control (PFC) frame duration using the F-Tile Ethernet Hard IP variant configured for 400GE-8 or 400GE-4? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may see the o_rx_pfc signal shows an incorrect duration that doesn’t match the received PFC control frame quanta values when back-to-back PFC frames are received on RX-MAC in the F-Tile Ethernet Hard IP using 400GE configurations. The incorrect duration is seen because of a problem in the F-Tile Ethernet Hard IP, where PFC indication is cleared in just 2-3 HIP cycles instead of maintaining the proper duration based on the received frame’s quanta field. This occurs only in 400GE configurations. Resolution There is a workaround implemented to handle PFC indication soft logic within the F-Tile Ethernet Hard IP. If you may need this workaround for the previous Quartus Prime Pro Edition software, please contact an Altera Representative and quote ID #15017410220. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Errata 15017410220 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']