Why do I see the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example packet generator send an extra packet of length >1518? - Why do I see the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example packet generator send an extra packet of length >1518? Description Due to a bug in the Low Latency 100G Ethernet Stratix® 10 FPGA IP Core Design Example fixed mode and incremental mode, you may see the packet generator send an extra packet of length >1518 in the Ethernet Link Inspector tool TX and RX Statistics section in Statistics Counters Tab (1519 - Max Byte Frames is incremented by 1). This problem will not affect the actual 100G Ethernet traffic. For example, when the packet range is set between 0x40 and 0x42 with total packets = 10, you could see an extra packet being sent, which increments Max Bytes Frames by 1. Resolution . Custom Fields values: ['novalue'] Troubleshooting FB: 1408590683; False ['Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']