Why do hardware tests fail for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? - Why do hardware tests fail for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3 and 23.4, hardware tests will fail when using the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example. Resolution To work around this problem, add the Quartus® Settings File (.qsf) constraints shown below to solve errors in packet transactions: set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to rx_serial_data -entity altera_eth_tse_hw set_instance_assignment -name HSSI_PARAMETER "rx_adapt_mode=RX_ADAPT_MODE_STATIC_EQ" -to rx_serial_data -entity altera_eth_tse_hw The problem will be fixed in future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16021929411 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']