Why do I see different Stratix® 10 Quartus® Prime Pro Edition Software generated DDR4 IBIS pin model at same bus signals ? - Why do I see different Stratix® 10 Quartus® Prime Pro Edition Software generated DDR4 IBIS pin model at same bus signals ? Description This is expected in the DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. The IBIS model is based on pin location and function in the design. In the x8/9 design, some of the DQ or Address/Command pins are located on a pin supporting DQS functionality (in x4 interfaces). The physical properties of the I/O pins that support both DQ and DQS functions are slightly different than the pins that only support DQ functions, so Quartus® Prime Pro Edition Software uses different models to improve the accuracy of the simulation. Resolution This is an example DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. You can see the mem_a(14) and mem_a(13) pins are assigned to the DQS functionality pin and have a different IBIS model name than other mem_a pins. mem_a(14)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(13)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(12)~pad sstl12_rtio_r34cp1_lv mem_a(16)~pad sstl12_rtio_r34cp1_lv mem_a(15)~pad sstl12_rtio_r34cp1_lv mem_a(2)~pad sstl12_rtio_r34cp1_lv mem_a(6)~pad sstl12_rtio_r34cp1_lv mem_a(0)~pad sstl12_rtio_r34cp1_lv mem_a(3)~pad sstl12_rtio_r34cp1_lv mem_a(7)~pad sstl12_rtio_r34cp1_lv mem_a(1)~pad sstl12_rtio_r34cp1_lv Custom Fields values: ['novalue'] novalue 1509874354 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']