Can a Global Clock (GCLK) be used as the input clock source for a non-DPA ALTLVDS_RX interface, in Stratix V, Arria V or Cyclone V devices? - Can a Global Clock (GCLK) be used as the input clock source for a non-DPA ALTLVDS_RX interface, in Stratix V, Arria V or Cyclone V devices? Description No, a Global Clock (GCLK) cannot be used as the input clock source for a non-DPA ALTLVDS_RX interface in Stratix ® V, Arria ® V or Cyclone ® V devices. However, due to a known issue in the Quartus ® II software version 13.0, no error or warning message is generated if this is implemented. Resolution This issue is fixed in Quartus II software version 13.0 SP1. A valid error message will be generated if a Global Clock (GCLK) is used as the input clock source for a non-DPA ALTLVDS_RX interface. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 13.0 ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']