Why do I see the unconstrained path at the Agilex™ 7 FPGA M-Series DDR5 EMIF IP interface? - Why do I see the unconstrained path at the Agilex™ 7 FPGA M-Series DDR5 EMIF IP interface? Description When you compile the design on the Timing analyzer tab, you may see the unconstrained path at the Agilex™ 7 FPGA M-Series DDR5 EMIF IP interface. Resolution DQS clock name has to be *dqs_t and *dqs_c at the top module to associate DQS as clock signals. For example //inout [ 4:0] MEM0_DQS_P, //inout [ 4:0] MEM0_DQS_N, inout [ 4:0] MEM0_dqs_t, inout [ 4:0] MEM0_dqs_c, Custom Fields values: ['novalue'] Troubleshooting 15017190099 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']