FPGA- SDC creation for 0.00039MHz clk - FPGA- SDC creation for 0.00039MHz clk I have to create the sdc description for 0.00039MHz which was generated using counter logic. FPGA_CLK is 26 MHz, from that i would like to specify the clk value in my sdc file i am trying to give this clk using the below command: create_generated_clock -divide_by 65536 -source [get_ports FPGA_CLK] -name Clkprescaler:Clockprescaler|divider[15] [get_registers {Clkprescaler:Clockprescaler|divider[15]}] But it is not taken by the tool, its still showing the error as unconstrainted. any suggestions? Re Replies: Re: FPGA- SDC creation for 0.00039MHz clk No, I have used the enable method. Thanks for the response Replies: Re: FPGA- SDC creation for 0.00039MHz clk As we do not receive any response from you on the previous answer that we have provided. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: FPGA- SDC creation for 0.00039MHz clk Is there any further question? Replies: Re: FPGA- SDC creation for 0.00039MHz clk Is there any further question? Replies: Re: FPGA- SDC creation for 0.00039MHz clk Is there any further question base on above? Replies: Re: FPGA- SDC creation for 0.00039MHz clk Instead of using a slow clock for your sensor detection module, you update it only when clk_en is high : always @(posedge clk or negedge reset_n) begin if (!reset_n) begin sensor_state <= 0; end else if (clk_en) begin sensor_state <= sensor_input; // Sample the sensor input at 390 Hz end end If you need to detect a rising edge of the sensor input, you can do: reg sensor_prev; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin sensor_prev <= 0; end else if (clk_en) begin sensor_prev <= sensor_input; end end wire sensor_rising_edge = clk_en & sensor_input & ~sensor_prev; This will trigger a pulse only when the sensor input rises at 390 Hz. Replies: Re: FPGA- SDC creation for 0.00039MHz clk In my design, the slower clock is used as clock for one module, in this rising edge we are detecting the sensor input. if we use the clk_en method how do we use this signal as clock? Regards, Abinaya Replies: Re: FPGA- SDC creation for 0.00039MHz clk A 0.00039 MHz clock translates to a period of approximately 2.56 milliseconds . This could lead to: Misinterpretation of timing constraints : The design tools may allocate unnecessarily large timing slacks, obscuring critical path analysis. Difficulties ensuring timing closure for faster clocks in the design. Replies: Re: FPGA- SDC creation for 0.00039MHz clk I believe that it is because you are constraining the clock to be too slow that is causing this problem. My suggestion is for you to use clock enable instead: Example 1: reg [16:0] counter; reg clk_en; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin counter <= 0; clk_en <= 0; end else if (counter == 127999) begin // Divide 50 MHz to 390 Hz counter <= 0; clk_en <= 1; end else begin counter <= counter + 1; clk_en <= 0; end end. Adjust 127999 if using a different base clock frequency. Example 2: Use the generated clk_en to enable the logic that would typically run on the 390 Hz clock: verilog always @(posedge clk or negedge reset_n) begin if (!reset_n) begin slow_logic_state <= 0; end else if (clk_en) begin slow_logic_state <= next_slow_logic_state; end end Thanks Replies: Re: FPGA- SDC creation for 0.00039MHz clk this value is used for some slower clk sensor rise fall detection. I need three slow clocks CLKBY4096 -- 0.00634MHz CLKBY16384 -- 0.00158MHz CLKBY65536 -- 0.00039MHz Also in sta report i am not seeing these clock values. instead it shows 0.01 MHz, 0.0MHz and the last one is not taking. How do i give the constraint for these small clk values? Regards, Abinaya Replies: Re: FPGA- SDC creation for 0.00039MHz clk base clk is FPGA_CLK which is already constrained.i don't know why the divider[15] is taken as the base type Replies: Re: FPGA- SDC creation for 0.00039MHz clk What does your base create_clock constraint look like? You can't create a generated clock if the base clock it references isn't constrained as well. The report there shows the base clock as unconstrained. Replies: Re: FPGA- SDC creation for 0.00039MHz clk Hi, if timing analysis detects an incorrect or not implementable constraint, it adds a message to timing analysis report. It should explain why your generated clock isn't accepted. I wonder what's the purpose of a 390 Hz clock in your design. In most cases, we'll use a clock enable in the respective master clock (26 MHz) domain instead, keeping a single synchronous clock domain.