Why the clock frequency of the Cyclone® V HPS EMAC emac*_tx_clk exported to the FPGA fabric shown as 100Mhz in timing analysis? - Why the clock frequency of the Cyclone® V HPS EMAC emac*_tx_clk exported to the FPGA fabric shown as 100Mhz in timing analysis? Description Due to a problem in the Quartus® Prime Starndard Edition Software version 20.1 and earlier, you can find GMII clock frequency is 100Mhz when enabling HPS EMAC and route it to FPGA in Cyclone® V SoC. Resolution To work around this problem in the Cyclone® V SoC HPS, you need to correct the period of emac*_tx_clk from 10ns to 8ns in cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces.sdc. Custom Fields values: ['novalue'] Troubleshooting 1508376740 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 20.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']