Why do Dual Simplex (DS) designs sometimes become stuck during the Dynamic Reconfiguration (DR) process when using the F-Tile Dynamic Reconfiguration Suite IP for dynamic reconfiguration in the Quartus® Prime Pro Edition software version 25.3? - Why do Dual Simplex (DS) designs sometimes become stuck during the Dynamic Reconfiguration (DR) process when using the F-Tile Dynamic Reconfiguration Suite IP for dynamic reconfiguration in the Quartus® Prime Pro Edition software version 25.3? Description Due to a problem in the F-Tile Dynamic Reconfiguration Suite IP in Quartus® Prime Pro Edition software version 25.3, you may encounter problems during dynamic reconfiguration of Dual Simplex (DS) designs, such as HDMI. The dynamic reconfiguration (DR) process may become stuck, causing the design to hang indefinitely. The only way to recover from this state is to power-cycle the board or reconfigure the Agilex™ 7 FPGA device. The reset sequence problem for the F-Tile Dynamic Reconfiguration Suite IP is isolated specifically for Dual Simplex designs dynamic reconfiguration. Resolution To work around this problem and prevent dynamic reconfiguration (DR) from hanging in Dual Simplex (DS) designs, it is recommended to apply both TX and RX reset, even if dynamic reconfiguration is only needed for the TX side or the RX side in dual simplex DR cases. For example, if you are dynamically reconfiguring between TX-only profiles or RX-only profiles, you should assert a reset on both TX and RX before performing dynamic reconfiguration to avoid this hang issue. This workaround is only required for Quartus® Prime Pro Edition software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: Troubleshooting 18043486789, 16028950213 ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs']