Why do CSR read/write accesses to the H-Tile Hard IP for Ethernet Stratix® 10 FPGA IP Core take more than 100 Avalon®-MM clock cycles (reconfig_clk)? - Why do CSR read/write accesses to the H-Tile Hard IP for Ethernet Stratix® 10 FPGA IP Core take more than 100 Avalon®-MM clock cycles (reconfig_clk)? Description CSR read/write accesses to the H-Tile Hard IP for Ethernet Stratix® 10 FPGA IP Core take more than 100 Avalon®-MM clock cycles (reconfig_clk) as shown in simulation. This is the expected behavior due to the 8-bit CSR interface on the H-tile Hard IP Ethernet Stratix 10 FPGA Core. Each user Avalon®-MM 32-bit interface read/write results in 32-bit to 8-bit bus data width conversion logic which causes the extra access latency. Note: The Low Latency 100G Ethernet Stratix® 10 FPGA IP Core (soft IP) CSR interface does not have this extra latency. Resolution Not Applicable Custom Fields values: ['novalue'] Troubleshooting 586226 False ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']