For DDR2 and DDR3 SDRAM Controller with UniPHY, SOPC Builder Designs Suffer Low Efficiency - For DDR2 and DDR3 SDRAM Controller with UniPHY, SOPC Builder Designs Suffer Low Efficiency
Description If you use SOPC Builder to instantiate a DDR2 or DDR3 SDRAM Controller with UniPHY IP core, you may find your design has low memory efficiency. Resolution To work around this issue, use the MegaWizard Plug-In flow to instantiate a DDR2 or DDR3 SDRAM Controller with UniPHY IP core.
Custom Fields values:
['novalue']
Troubleshooting
novalue
True
['novalue']
['FPGA Dev Tools Quartus II Software']
11.0
10.0
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document