Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals? - Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals? Description Due to a problem in the Quartus® II software version 11.1 and later, the DDR3 UniPHY-based memory controllers with the efficiency monitor enabled incorrectly use the Avalon®-MM signal names (e.g. avl_waitrequest ) instead of Avalon-ST signal names (e.g. avl_ready ). There is a problem during the generate stage of the controller where the Avalon-MM interface of the efficiency monitor is exported instead of the Avalon-ST interface of the controller. Resolution This issue is fixed in the Quartus II software version 12.1 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 11.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']