High Level Synthesis Advanced Optimization Techniques - This advanced course focuses on performance critical optimization techniques for High Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition. FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA This advanced course focuses on performance critical optimization techniques for High Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition. It is designed for engineers who have completed the “HLS for FPGA Acceleration” course (or possess equivalent hands-on HLS experience) and want to push designs from functional but slow to near hand optimized RTL performance. Rather than re-introducing HLS concepts from scratch, the course dives deeply into how the HLS compiler makes architectural decisions, how to guide those decisions explicitly, and how to optimize throughput, latency, memory bandwidth, and resource utilization on Altera FPGA fabrics. Significant emphasis is placed on understanding compiler reports, identifying and classifying performance bottlenecks, and mastering the tradeoffs involved in aggressive optimization. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless High Level Synthesis Advanced Optimization Techniques Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA 2 Days No No English Offering Brief Production Windows,Linux a1JUi000009ZaD7MAK Experience writing, compiling, and simulating HLS components in the Altera HLS Compiler Hardware and Software Engineers, FPGA Designers, System Architects, Managers What's Included PDF of slides, lab manual and lab files where applicable Ordering Information High Level Synthesis Advanced Optimization Techniques a1JUi000009ZaD7MAK Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-07-16T20:44:26.000+0000 This advanced course focuses on performance critical optimization techniques for High Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition. Partner Solutions