Design works in ASE not on FPGA - Design works in ASE not on FPGA Hi, Our design works in the ASE simulation environment. But it doesn't work on FPGA. Timing constraints are being met. Please let us know as to what we might be missing / going wrong. Thanks Replies: Re: Design works in ASE not on FPGA Hi, Sorry for the delayed response. We realised that the FIFO IP was not working when we run on the FPGA. So, we used our queues and now we're able to get the results on FPGA. Thanks, Navaneeth M Replies: Re: Design works in ASE not on FPGA Hi, We do not receive any response from you on the previous reply provided. Please login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, May I know if you have any updates? Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to. Is it possible to share a tar.gz file of the Quartus project? Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/simulation-nativelink-howto.html?wapkw=quartus%20simulation Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, Sorry for the delayed response. Can you please try with https://drive.google.com/file/d/1K9rg_u6i57mGkBegACfYQz5UjMJiNV8N/view?usp=share_link ? Steps to run ASE ( after extracting the tar.gz file 1. cd Capstone-Streaming-DMA-AFU 2. afu_sim_setup --source=./hw/rtl/filelist.txt build_ase_dir 3. cd build_ase_dir 4. make -j16 ( takes around 5 minutes ) 5. two screen sessions are needed On first: 1. make sim -j16 2. < copy the export path > On second: 1. cd sw 2. < paste the export path > 3. make USE_ASE=1 4. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0 Steps to run on FPGA: 1. cd Capstone-Streaming-DMA-AFU 2. afu_synth_setup --source=./hw/rtl/filelist.txt build_synth_dir 3. cp afu_default.qsf build_synth_dir/build/ 4. cp flame-job-script.sh build_synth_dir 5. cd build_synth_dir 6. ./flame-job-script.sh ( takes around 2 hours ) 7. fpgaconf streaming_dma_afu.gbs 8. cd ../sw 9. make 10. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0 Thanks, Navaneeth M Replies: Re: Design works in ASE not on FPGA Hi, I've included the modules in hw/rtl/ but I still see some errors related to it. Error(13406): Verilog HDL error at afu.sv(31): object "ccip_avmm_pkg" is not declared Error(13406): Verilog HDL error at afu.sv(139): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(139): range must be bounded by constant expressions Error(14395): Verilog HDL error at afu.sv(140): CCIP_AVMM_REQUESTOR_WR_ADDR_WIDTH is not a constant Error(17457): Verilog HDL error at afu.sv(140): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(142): object "CCIP_AVMM_REQUESTOR_BURST_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(142): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(147): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(147): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(149): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(149): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(150): object "CCIP_AVMM_REQUESTOR_RD_ADDR_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(150): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(153): object "CCIP_AVMM_REQUESTOR_BURST_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(153): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(156): object "CCIP_AVMM_MMIO_DATA_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(156): range must be bounded by constant expressions Error(13406): Verilog HDL error at afu.sv(158): object "CCIP_AVMM_MMIO_DATA_WIDTH" is not declared Error(17457): Verilog HDL error at afu.sv(158): range must be bounded by constant expressions Error(16827): Verilog HDL error at ccip_std_afu.sv(34): cannot open include file cci_mpf_if.vh Error(13406): Verilog HDL error at ccip_std_afu.sv(35): object "cci_mpf_csrs_pkg" is not declared Received this critical warning: Critical Warning(125091): Tcl error: couldn't read file "../../hw/rtl/BBB_ccip_avmm/hw/par/ccip_avmm_addenda.qsf": no such file or directory while executing "source ../../hw/rtl/BBB_ccip_avmm/hw/par/ccip_avmm_addenda.qsf" (file "../hw/afu.qsf" line 6) The project I received doesn't have the folder ../../hw/rtl/BBB_ccip_avmm/hw/par/ Is this required in the project? Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, We haven't received any such errors. The ccip_std_afu is located in the hw/rtl/ccip_std_afu.sv file. We're using the streaming-dma-afu BBB as our base design and we've included our files - split.sv and cmm_top.sv ( our matrix multiplier verilog code file ) - in hw/rtl/QSYS_IPS/avst_decimator folder. Replies: Re: Design works in ASE not on FPGA Hi Navaneeth, Thank you for the response. I received below error, is there anything I should re-generate/import? Error(16045): Instance "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim|ccip_std_afu" instantiates undefined entity "ccip_std_afu" Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim|ccip_std_afu" Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim" Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu" Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, We are using the following version of Quartus: Info: Running Quartus Prime Shell Info: Version 18.1.2 Build 277 02/12/2019 Patches 2.02,2.03,2.06 SJ Pro Edition Apologies for the misleading name Regards, Navaneeth M Replies: Re: Design works in ASE not on FPGA Hi, Are you using Quartus Prime Pro v19.2? Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, PFA the google drive link to the .qar file. dcp_19_2_0_57.qar Replies: Re: Design works in ASE not on FPGA Hello, Could you share the .qar file? To do this, go to Project->Archive Project Regards, Nurina Replies: Re: Design works in ASE not on FPGA Hi, Can you share with us the code and step to duplicate the issue so that we can further look into the issue? Replies: Re: Design works in ASE not on FPGA https://youtu.be/Mftgi318Nrc Replies: Re: Design works in ASE not on FPGA Hi, Sure thanks. We're targetting Stratix 10 family. And the design is a 16x16 Matrix multiplier. The issue is - when we configure the FPGA with the GBS file ( that has met timing constraints ) and then run the software, we get all zeroes as output but on ASE, it gives the correct output. We're using the streaming dma afu as the basic building block. And we've included our design in the avst_decimator.sv file ( which was doing a loopback ). Can you please by mentioning a list of possible things we can do to debug this issue? Also, can you please let us know if there's a way to view waveform generated in real time on FPGA? Replies: Re: Design works in ASE not on FPGA Hello, Please give us more information, otherwise I can't assign this case to the correct person. regards, Farabi Replies: Re: Design works in ASE not on FPGA Definitely need more info here. What is the design? What device are you targeting? What is not working? Can you provide some code? The people in this forum are good but we aren't mind readers! - 2022-10-26