Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O? - Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O? Description UniPHY-based memory controllers with the On-chip Debug Toolkit enabled will have an Avalon®-MM slave port exported to the top level of the example design. The additional pins required by the Avalon-MM slave port could lead to "No Fit" errors for some smaller package sizes. Resolution To remove the Avalon-MM slave port, disable the On-chip Debug Toolkit and regenerate the example design, or manually remove the Avalon-MM slave port from the top level. This issue has been fixed in the Quartus® II software 13.1 version. Custom Fields values: ['novalue'] Troubleshooting 2205801588 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']