Does the Quartus II synthesis support event controls in Verilog HDL? - Does the Quartus II synthesis support event controls in Verilog HDL?
Description No, the Quartus® II Integrated Synthesis does not support event controls in Verilog HDL. For example, the code below synthesizes only one register, although the Quartus II synthesis does not issue an error: module lab0_uart( input clk_i, input rx_i, output reg tx_o ); always @(posedge clk_i) begin tx_o <= repeat(2000) @(posedge clk_i) rx_i; end endmodule Resolution To avoid this behavior, do not use event controls in Verilog HDL. An error indicating that this syntax is not supported is scheduled to be added to a future release of the Quartus II software.
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Troubleshooting
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False
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['FPGA Dev Tools Quartus II Software']
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No plan to fix
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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