Why does the Intel® Stratix®10 Hard IP for PCIe* report incorrect link widths? - Why does the Intel® Stratix®10 Hard IP for PCIe* report incorrect link widths?
Description Due to an encoding problem with the link acknowledge logic in Intel® Stratix® 10 H-Tile ES2 devices, link widths will be incorrectly acknowledged as shown below: Actual Link Width Link Acknowledge x1 x16 x2 x1 x4 x2 x8 x4 x16 x8 Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.
Custom Fields values:
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Troubleshooting
FB: 502069, 508093;
True
['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express']
['FPGA Dev Tools Quartus® Prime Software Pro']
19.1
17.0
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-09
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