Why does the PHY Lite for Parallel Interfaces IP Parameter Editor GUI not produce any error message when input or bidirectional pins are placed in the same lane as RZQ using POD I/O standards? - Why does the PHY Lite for Parallel Interfaces IP Parameter Editor GUI not produce any error message when input or bidirectional pins are placed in the same lane as RZQ using POD I/O standards? Description Due to a problem in Quartus® Prime Pro Edition Software version 24.3, you might see that the PHY Lite for Parallel Interfaces IP Parameter Editor GUI does not produce an error message when input or bidirectional pins are placed in the same lane as the RZQ pin, and the I/O standard is either 1.1-V POD or 1.2-V POD. When lane 3 is used (RZQ pin index 38), the Quartus ® compilation fails with the following error message: Error(12406): Port I of I/O buffer "phylite_ph2_0_example_design|phylite_ph2_0_example_design|core|arch_inst|phylite_iobufs_inst|ibuf_rzq.ibuf_inst_rzq" must be connected to a top-level pin However, when lane 5 is used (RZQ pin index 62), the Quartus ® compilation passes when it should fail. Resolution To work around this problem, use a different lane than the RZQ lane. No input or bidirectional pins can be placed in the same lane as RZQ, i.e., lane 3 (pin index 38) or lane 5 (pin index 62), for all supported I/O standards. Only output pins can be placed in the same lane as the RZQ pin. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14023449228 False ['PHY Lite for Parallel Interfaces IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ FPGA Portfolio'] ['novalue'] ['novalue'] ['novalue']