When using the Intel® Arria® 10 PCI Express IP core in Avalon-ST mode, why do I see a 1 clock latency between tx_cred_fc_sel and tx_cred_hdr_fc/tx_cred_data_fc outputs in simulation but a 2 clock latency in actual hardware? - When using the Intel® Arria® 10 PCI Express IP core in Avalon-ST mode, why do I see a 1 clock latency between tx_cred_fc_sel and tx_cred_hdr_fc/tx_cred_data_fc outputs in simulation but a 2 clock latency in actual hardware? Description When using the Arria® 10 HIP for PCI Express® in Avalon®-ST mode, you will see a latency difference between simulation and hardware. This behavior is due to a problem with the Quartus® II software. The correct behavior is that seen in hardware, which is 2 pld_clk cycles of delay between the assertion of tx_cred_fc_sel and the appearance of corresponding data on tx_cred_hdr_fc and tx_cred_data_fc. Resolution To work around this problem, add a small delay to the tx_cred_fc_sel signal in your testbench. For example: assign #1 tx_cred_fc_sel-to-core = tx_cred_fc_sel; Custom Fields values: ['novalue'] Troubleshooting 2205868221 False ['Clock Source'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']