JPEG-E-S: Baseline JPEG Encoder - The JPEG-E-S IP core supports the Baseline Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient hardware JPEG encoder with low latency. It produces compressed JPEG… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Intel® MAX® 10 FPGA This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with remarkably low processing latency. The JPEG-E-S encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. The compact encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST. The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model. Video and Image Processing Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Transportation Wireless JPEG-E-S: Baseline JPEG Encoder Key Features Supports ISO/IEC 10918-1 Baseline JPEG, single-frame and Motion JPEG, 8-bit samples, up to 4 components, all scan configs, markers, and programmable tables. Offering Brief Yes Yes No Yes Verilog Intel® MAX® 10 FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U7GMAU What's Included FPGA netlist Ordering Information JPEG-E-S a1JUi0000049U7GMAU Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T22:35:41.000+0000 The JPEG-E-S IP core supports the Baseline Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient hardware JPEG encoder with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8-bit color samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. Once configured, it operates standalone without host intervention. Integration is simple via AMBA®: AXI Streaming for pixels/compressed data and a 32-bit APB slave for registers. Optional AXI Streaming allows timestamps or metadata insertion. CAST offers IP Integration Services delivering complete JPEG subsystems with video interfaces, UDP/IP or Transport Stream stacks, and other IP. Designed with industry best practices, its reliability is proven through verification, production use, and a bit-accurate software model. Partner Solutions