Incorrect Description of edgecapture Bit Clearing - Incorrect Description of edgecapture Bit Clearing Description In the PIO Core chapter of the Embedded Peripherals IP User Guide , a footnote to Table 10-2 incorrectly states “Writing any value to edgecapture clears all bits to 0.” This statement is only true if the Enable bit-clearing for edge capture register option is turned off. Resolution The footnote should read as follows: If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']