Incorrect Clock Uncertainty in UniPHY External Memory Interfaces - Incorrect Clock Uncertainty in UniPHY External Memory Interfaces Description A clock uncertainty related to the read FIFO clocked by DQS can result in inaccurate setup and hold slack values. Resolution The workaround for this issue is to manually edit the PHY .sdc file located in the < variation_name >/ constraints / directory, and add the following two lines to the Multicycle Constraints section of the file: set_max_delay -from *ddio_in_inst_regout* -0.05 set_min_delay -from *ddio_in_inst_regout* [expr - 0.05]. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']