DDR2 Interfaces Using Soft Memory Controller May Not Close Timing When Targeting Arria V or Cyclone V Devices - DDR2 Interfaces Using Soft Memory Controller May Not Close Timing When Targeting Arria V or Cyclone V Devices Description This problem affects DDR2 and LPDDR2 products. Interfaces using the soft memory controller may fail to close timing on Arria V and Cyclone V devices. Resolution The workaround for this issue is to use a different fitter seed. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']