Agilex™ 7 - FPGA F-Tile SDI II FPGA IP Multi Rate Parallel Loopback Without External VCXO Onboard - This design example showcases the Multi-Rate Parallel Loopback Without External VCXO onboard design implemented on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit. The design demonstrates SDI loopback feature using the SDI II FPGA IP - 2026-06-03
- Version
- 26.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Agilex Families > Agilex 7
- Resource Type
- Source Name
- Markdown