Agilex™ 7 FPGA - AN901: Implementing Synchronized ADC Dual Link Design with JESD204C RX IP Core v3 - This design demonstrates how to scale a single-link JESD204C Intel® FPGA IP core example design generated by the Intel® Quartus® Prime software into a multipoint link system. In JESD204C, a single link consists of one or more high-speed transceiver lanes (channels). - 2024-05-22
- Version
- 24.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Agilex Families > Agilex 7
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- Markdown