Agilex™ 7 FPGA - F-Tile JESD204C Multi-link Reference Design - This design serves as a reference to scale up the single link in the F-Tile JESD204C Intel FPGA IP core design example generated from the Intel Quartus Prime software to handle multipoint link system. A single link in JESD204C has one or more high speed transceiver lanes or channels. - 2026-04-22

Version

25.1.1