Agilex™ 5 FPGA - Hello world and OCM memory test design on Nios® V/c Processor - This example design includes a NIOS V/c embedded processor connected to the OCM and JTAG UART IP. - 2024-11-22
- Version
- 24.2.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Agilex Families > Agilex 5 > E-Series
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown