Agilex™ 7 FPGA R-Tile PCIe Lane Margining Tool Design Example - This design enables a user to perform lane margining on the R-Tile PCIe HIP. Control to the design is supported by the PCIe link itself. A small application will need to be developed to configure, launch, and retrieve lane margining results. Pseudo code is included in this user guide as an example for the application. The small application is based on the PCIe Linux Kernel driver that ships with our R-Tile PCIe PIO Design Example. There are two major components to this tool: FPGA RTL Design and the lane margining algorithm written in C++. The solution includes source code. The source code will allow a user to customize the tool for their specific R-Tile use case. - 2024-03-08

Version

23.2.0