Agilex™ 7 FPGA - Nios® V/c Processor with PIO and OCM - This design example includes a Nios® V/c compact embedded processor connected to the Parallel Input Output (PIO) IP, On-Chip RAM JTAG UART IP and System ID Peripheral core IP. - 2024-03-05
- Version
- 24.1.0
- Product Type
- Device Families > Agilex Families > Agilex 7 > F-Series
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown