Agilex™ 7 FPGA - Nios® V/m EMIF Data Mover Design - The Nios® V processor IP interacts with the onboard memory (DDR) using an EMIF controller. - 2024-10-29
- Version
- 24.2.0
- Product Type
- Device Families > Agilex Families > Agilex 7 > F-Series
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown