MAX® 10 FPGA – DDR3 Memory Test with the Nio® II Processor Design Example - This design example demonstrates how to run a memory test on a particular memory address using the Nios® II processor eclipse memory test template. The purpose of this design example is to help users determine which memory address fails on DDR3 read/write transactions. - 2017-02-20
- Version
- 16.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > MAX Families > MAX 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown