MAX® 10 FPGA – Using Tightly Coupled Memory with the Nios® II Processor for Terasic's MAX® 10 FPGA NEEK Board Design Example - This design example shows the use of tightly coupled memory (TCM) in designs that include the Nios® II processor. By enabling the processor's TCM primary, the Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance-critical applications. The Nios II Ethernet Simple Socket Server for Terasic's MAX® 10 FPGA NEEK Board provides the hardware platform on which the design runs. - 2016-12-18

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16.0.0