MAX® 10 FPGA – Using Tightly Coupled Memory with the Nios® II Processor for Terasic's MAX® 10 FPGA NEEK Board Design Example - This design example shows the use of tightly coupled memory (TCM) in designs that include the Nios® II processor. By enabling the processor's TCM primary, the Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance-critical applications. The Nios II Ethernet Simple Socket Server for Terasic's MAX® 10 FPGA NEEK Board provides the hardware platform on which the design runs. - 2016-12-18
- Version
- 16.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > MAX Families > MAX 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown