Stratix® 10 FPGA – Ultra Low Latency Ethernet 10G for Altera® Devices Reference Design - The Ultra Low Latency Ethernet 10G reference design demonstrates a low latency 10G Ethernet solution for Stratix® 10 devices. This reference design, which uses 10GBASE-R PHY with IEEE 1588v2 mode, is capable of achieving a lower round-trip latency of 171.0 ns compared to the 10GBASE-R Ethernet design example for Stratix® 10 devices with 246.5 ns. - 2018-06-05
- Version
- 18.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Stratix Families > Stratix 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown