Cyclone® V FPGA – UART RS-232 Maximum Baud Rate Reference Design - This example is a test functionality for the UART RS-232 Serial Port IP which contains a Nios® II processor and Dual UART RS-232 IP. The design example implements a basic UART RS-232 functionality of a variable baud rate on a real-time basis. This means the developer can set the required baud rate of data transfer from the Nios II processor application. Furthermore, this design demonstrates a standard method of developing a UART application with the Nios II processor. - 2016-12-23
- Version
- 16.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > Cyclone Families > Cyclone V
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown