Arria® 10 FPGA – Two x8 Lane JESD204B (Duplex) IP Core Multi-Device Synchronization Using a Nios® II Processor Reference Design - This reference design demonstrates the implementation of two x8 lane JESD204B (duplex) IP core synchronization in Arria® 10 devices through an FMC loopback card. The main purpose is to emulate the interface between one converter card with two x8 lane JESD204B (duplex) IP cores. - 2017-05-25

Version

17.0.0