Arria® 10 FPGA – Two x8 Lane JESD204B (Duplex) IP Core Multi-Device Synchronization Using a Nios® II Processor Reference Design - This reference design demonstrates the implementation of two x8 lane JESD204B (duplex) IP core synchronization in Arria® 10 devices through an FMC loopback card. The main purpose is to emulate the interface between one converter card with two x8 lane JESD204B (duplex) IP cores. - 2017-02-22
- Version
- 16.1.2
- Product Type
- Device Families > Arria Families > Arria 10
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown