Stratix® 10 FPGA – TX PAM4 2 x 51 Gbps with SMA Design Example - This design example demonstrates the Stratix® 10 FPGA TX PAM4 2 x 51 Gbps channels interface with SMA. It has the Transceiver Toolkit enabled for bit error rate (BER) testing and link status monitoring. This design has been tested on the Stratix® 10 TX Signal Integrity Development Kit with SMA cables. - 2019-05-08
- Version
- 18.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Stratix Families > Stratix 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown