Stratix® V FPGA – DSP Multichannel FIR Using Verilog Design Example - AN639: Inferring Stratix® V DSP Blocks for FIR Filtering Applications contains nine example projects. This is the fifth project: StratixV_DSP_FIR/Verilog/multichannel_fir/18x18/systolic_chainout_adder/chan4_fir - 2017-03-06

Version

16.1.0