Stratix® V FPGA – DSP Interpolation FIR Using Verilog Design Example - AN639: Inferring Stratix® V DSP Blocks for FIR Filtering Applications contains nine example projects. This is the fourth project: StratixV_DSP_FIR/Verilog/interpolation_fir/18x18/systolic_chainout_adder/int4_chan4_fir - 2017-03-06

Version

16.1.0