Stratix® V FPGA – DSP Decimation FIR Using Verilog Design Example - AN639: Inferring Stratix® V DSP Blocks for FIR Filtering Applications contains nine example projects. This is the third project: StratixV_DSP_FIR/Verilog/decimation_fir/18x18/sum_of_2_chainout_adder/dec4_chan4_fir - 2017-02-14

Version

16.1.0