Stratix® V FPGA – DSP Basic Symmetric FIR Using Verilog Design Example - AN639: Inferring Stratix® V DSP Blocks for FIR Filtering Applications contains nine example projects. This is the second project: StratixV_DSP_FIR/Verilog/basic_fir_symmetric/18x18/systolic_chainout_adder/single_fir - 2017-02-14

Version

16.1.0