Stratix® 10 FPGA – TX PAM4 8 x 51 Gbps with QSFPDD 1x1 Interface Design Example - This design example demonstrates the Stratix® 10 FPGA TX PAM4 8 x 51 Gbps channels interface with QSFPDD 1x1 modules. It has the Transceiver Toolkit enabled for bit error rate (BER) testing and link status monitoring. This design has been tested on the Stratix® 10 TX Signal Integrity Development Kit with QSFPDD loopback module. - 2019-05-08

Version

18.1.0