Stratix® 10 FPGA – Serial Flash Mailbox Client Altera® FPGAs IP Core Design Example - This reference design implements the Stratix® 10 Serial Flash Mailbox Client Altera® FPGAs IP core to perform general-purpose memory operations such as read flash device ID, perform sector erase on flash devices, and read and write data from and to flash devices. Other than that, it also shows the flow to write Raw Programming Data (.rpd) files into flash devices using the Stratix® 10 Serial Flash Mailbox Client Altera® FPGAs IP Core. - 2018-11-27

Version

18.0.0