Stratix® 10 FPGA – IOPLL Reconfiguration MIF Streaming Design Example - This design demonstrates the implementation of the I/O PLL reconfiguration dynamically through MIF streaming using the IOPLL Reconfig Altera® FPGAs IP core using predefined settings saved in an on-chip RAM. You need to generate a .mif file containing these pre-defined configurations. - 2017-10-27

Version

17.1.0