Stratix® 10 FPGA – IOPLL Reconfiguration Clock Gating Design Example - This design demonstrates the implementation of the I/O PLL clock gating reconfiguration using the IOPLL Reconfig Altera® FPGAs IP core. You can gate (disable) and un-gate (enable) the I/O PLL output clock 0 to output clock 7 of the I/O PLL. - 2017-10-27

Version

17.1.0